library ieee;
use ieee.std_logic_1164.all;

entity Decoding_Circuit is
   Port(
       OrFetchSrc, OrFetchDst, OrDst, OrResult, OrZ, OrNZ, OrJmp, ZFlag, Noob, PLAout:IN std_logic;
       NextAddressField                             :IN std_logic_vector (6 downto 0);
       PLA                                          :IN std_logic_vector(6 downto 0);  -- TEMP
       IR                                           :IN std_logic_vector (31 downto 0);
       MuAR                                         :OUT std_logic_vector(6 downto 0)
       );
end Decoding_Circuit;


architecture a of Decoding_Circuit is
begin
    -- MuAR(0)
    MuAR(0) <= NextAddressField(0) 
    or 
    (OrFetchSrc and ((not IR(31) and IR (30)) and (not IR(23)))) 
    or 
    (OrFetchDst and ((not Noob) or (IR(31) and (not IR(30))))) 
    or 
    (OrDst and (not IR(11))) 
    or 
    (OrResult and (IR(10) or IR(11))) 
    or 
    (OrZ and ZFlag) 
    or 
    (OrNZ and not ZFlag) 
    or 
    (OrJmp and ((not IR(11)) and IR(10))) 
    or 
    (PLAout and PLA(0));
    -- MuAR(1)
    MuAR(1) <= NextAddressField(1) 
    or 
    (OrFetchSrc and ((not IR(31) and IR (30)) and (IR(22) or IR(23)))) 
    or 
    (OrDst and (IR(10) or IR(11))) 
    or 
    (PLAout and PLA(1));
    -- MuAR (6 downto 2)
    MuAR(6) <= NextAddressField(6) or (PLA(6) and PLAout);
    MuAR(5) <= NextAddressField(5) or (PLA(5) and PLAout);
    MuAR(4) <= NextAddressField(4) or (PLA(4) and PLAout);
    MuAR(3) <= NextAddressField(3) or (PLA(3) and PLAout);
    MuAR(2) <= NextAddressField(2) or (PLA(2) and PLAout);
end a;